SIL Verification

Safety Instrumented Function (SIF)

SIL Verification

Safety Integrity Level; or SIL Verification demonstrates the capability of a Safety Instrumented Function (SIF) in accordance with IEC 61508 and IEC 61511 against the following requirements:

– Quantifying the effect of random hardware failures (Probability of Failure on Demand (PFD) or the Average Frequency of Dangerous Failures (PFH);

– Hardware safety integrity architectural constraints (Safe Failure Fraction (SFF), Hardware Fault Tolerance (HFT), Element Type A or B);

– Systematic capability;

– Common Cause Failure (CCF).

 

Methods of SIL Verification

SIL Verification can be carried out using various modelling techniques including Reliability Block Diagram (RBD), Fault tree Analysis (FTA) and Failure Mode and Effect Analysis (FMEA). Where the SIF fails to achieve the target failure measure or SIL, a sensitivity analysis can be carried out to demonstrate the effect of modifying certain factors. This includes the following factors:

– Maintenance strategy (repair time and proof test frequency);

– System architecture;

– Implementing diagnostic mechanisms;

– Minimising CCF.

 

Example of a RBD